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PI90SD1636C
SERDES Gigabit Ethernet Transceiver
Features
* IEEE 802.3z Gigabit Ethernet Compliant * Supports 1.25 Gbps Using NRZ Coding over uncompensated twin coax cable * Fully integrated CMOS IC * Low Power Consumption * ESD rating >2000V (Human Body Model) or > 200V (Machine Model) * 5-Volt Input Tolerance * Pin-Compatible with Agilent HDMP1636A/HDMP- 1646A and Vitesse VSC7123 transceivers (see Appendix A) * Packaging (Pb-free & Green available): - 64-pin LQFP (FC) - 64-pin LQFP (FD)
Description
The PI90SD1636C is a single chip, Gigabit Ethernet transceiver. It performs all the functions of the Physical Medium Attachment (PMA) portion of the Physical layer, as specified by the IEEE 802.3z Gigabit Ethernet standard. These functions include parallelto-serial and serial-to-parallel conversion, clock generation, clock data recovery, and word synchronization. In addition, an internal loopback function is provided for system debugging. The PI90SD1636C is ideal for Gigabit Ethernet, serial backplane and proprietary point-to-point applications. The device supports 1000BASE-LX and 1000BASE-SX fiber-optic media, and 1000BASE-CX copper media. The transmitter section of the PI90SD1636C accepts 10-bit wide parallel TTL data and converts it to a high speed serial data stream. The parallel data is encoded in 8b/10b format. This incoming parallel data is latched into an input register, and synchronized on the rising edge of the 125 MHz reference clock supplied by the user. A phase locked loop (PLL) locks to the 125 MHz clock. The clock is then multiplied by 10 to produce a 1.25 GHz serial clock that is used to provide the high speed serial data output. The output is sent through a Pseudo Emitter Coupled Logic (PECL) driver. This output connects directly to a copper cable in the case of 1000BASE-CX medium, or to a fiber optic module in the case of 1000BASE-LX or 1000BASE SX fiber optic medium. The receiver section of the PI90SD1636C accepts a serial PECLcompatible data stream at a 1.25 Gbps rate, recovers the original 10-bit wide parallel data format, and retimes the data. A PLL locks onto the incoming serial data stream, and recovers the 1.25 GHz high speed serial clock and data. This is accomplished by continually frequency locking onto the 125 MHz reference clock, and by phase locking onto the incoming data stream. The serial data is converted back to parallel data format. The `comma' character is used to establish byte alignment. Two 62.5 MHz clocks, 180 degrees out of phase, are recovered. These clocks are alternately used to clock out the parallel data on the rising edge. This parallel data is sent to the user in TTL-compatible form.
Applications
* * * * Gigabit Ethernet Serial Backplane Proprietary point-to-point applicaitons Passive Optical Networks
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Functional Block Diagram
EWRAP
10
TX<9:0>
Input Data Latch
10
Shift Registers
DOUT+ DOUT-
TX_CLK
TX PLL Clock Generator
62.5 MHz RX_CLK<1> RX_CLK<0> 62.5 MHz /2
125 MHz
10
RX<9:0>
Output Latch
RX PLL Clock Recovery
10
INPUT SELECTOR
EN_CDET COM_DET
FRAME ENABLE
10
Shift Registers
DIN+ DIN-
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Pin Configuration
GND_RX_ESD VCC_RX_ESD VCC_RX_ESD GND_TX_HS VCC_TX_ECL VCC_TX_HS
GND_RXA
GND_RXF
VCC_RXA
VCC_RXA
DOUT+
DOUT-
DIN+
DIN-
VCC_RXF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GND_ESD TX<0> TX<1> TX<2> VCC_ESD TX<3> TX<4> TX<5> TX<6> VCC_ESD TX<7> TX<8> TX<9> GND_ESD GND_TXA NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC COM_DET GND_RXT RX<0> RX<1> RX<2> VCC_RXT RX<3> RX<4> RX<5> RX<6> VCC_RXT RX<7> RX<8> RX<9> GND_RXT
GND_RXD
GND_TXD
VCC_RXD
VCC_TXD
EWRAP
NC
RX_CLK<1>
RX_CLK<0>
VCC_RXD
EN_CDET
Table 1. I/O Type Definitions
Type TTL_IN TTL_OUT HS_IN HS_OUT P Definition TTL Input TTL Output Hight-Speed Input High-Speed Output Power Ground
VCC_TXA
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SIG_DET
GND_RX
VCC_RX
TX_CLK
NC
NC
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Table 2. Pin Description
Name GND_ESD VCC_ESD TX<0> TX<1> TX<2> TX<3> TX<4> TX<5> TX<6> TX<7> TX<8> TX<9> GND_TXA VCC_TXA NC EWRAP VCC_TXD GND_TXD TX_CLK VCC_RXD GND_RXD EN_CDET Pin # 1, 14 5, 10 2 3 4 6 7 8 9 11 12 13 15 18 16, 17,27, 48, 49 19 20 21 22 23 28, 25 24 Type P Description Power and ground pairs for pad ESD structure.
TTL_IN
0-bit parallel data input pins. This data should be 10b/8b encoded. The least significant bit is TX<0> and is transmitted first.
P NC TTL_IN
Power and ground pair for TX PLL analog circuits. No Connect Wrap Enable. This pin is active HIGH. When asserted, the high-speed serial data are internally wrapped from the transmitter serial data output back to the receiver data input. Also, when asserted, DOUT are held static at logic 1. When deasserted, DOUT and .DIN are active. Power and ground pair for TX digital circuits. Reference clock and transmit byte clock. This is a 125 MHz system clock supplied by the host system. On the positive edge of the clock, the input data, TX<9:0>, are latched into the register. This clock is multiplied by 10 internally, to generate the transmit serial bit clock. Power and ground pair for digital circuits in the receiver portion. Comma Detect Enable. This pin is active HIGH. When asserted, the internal byte alignment function is turned on, to allow the clock to synchronize with the comma character (0011111XXX). When de-asserted, the function is disabled and will not align the clock and data. In this mode COM_DET is set to LOW. Signal Detect. This pin is active HIGH. It indicates the loss of input signal on the high-speed serial inputs, DIN. SIG_DET is set to LOW when differential inputs are less than 50 mV. Power and ground pair for the clock signal of the receiver portion. Receiver Byte Clocks. Two 180 degrees out-of-phase 62.5 MHz clock signals that are recovered by the receiver section. The received bytes are alternately clocked by the rising edges of these signals. The rising edge of RX_CLK<1> aligns with a comma character when detected.
P
TTL_IN
P
TTL_IN TTL_ OUT P TTL_ OUT
SIG_DET VCC_RX GND_RX RX_CLK<1> RX_CLK<0>
26 29 32 30 31
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Table 2. Pin Description (Continued.)
Name GND_RXT VCC_RXT RX<9> RX<8> RX<7> RX<6> RX<5> RX<4> RX<3> RX<2> RX<1> RX<0> COM_DET VCC_RXF GND_RXF DINDIN+ VCC_RXESD GND_RXESD VCC_RXA GND_RXA VCC_TX_ECL DOUTDOUT+ VCC_TX_HS GND_TX_HS Pin# 33 46, 37, 42 34 35 36 37 38 39 40 41 43 44 45 47 50 51 52 54 53,55 56 57, 59 58 60 61 62 63 64 P P P HS_OUT P P Type Description Power and ground pairs for ESD structure.
TTL_OUT
Received Parallel Data Output. RX<0> is the least significant bit and is received first. When DIN lose input data, all RX pins will be held HIGH.
TTL_OUT P HS_IN
Comma detect. This pin is active HIGH. When asserted, it indicates the detection of comma character (0011111XXX). It is active only when EN_CEDT is enabled. Power and ground pair for the front-end of the receiver section. High-speed serial data input. Serial data input is received when EWRAP is disabled. Power and ground pair for ESD structure. Power and ground pair for analog circuits of the receiver section. Power supply to line driver circuits. Ground supply is from pin 64. High-speed serial data output. These pins are active when EWRAP is disabled and are held static at logic 1 when EWRAP is enable. Power and ground pair for high-speed transmit logic in the parallel-to-serial section.
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Functional Block Description
Input Data Latch
The input data latch block latches the 10-bit TTL input parallel byte, TX<9:0>, on the rising edge of the 125 MHz user-provided TX_CLK into the holding registers.
Parallel-to-Serial Converter
The received 10-bit TTL parallel input byte is converted to serial PECL level data stream by the parallel-to-serial block, and is transmitted differentially to the line driver block at 1.25 Gbps. The 8b/10b encoded data is transmitted sequentially with bit 0 being sent first.
Clock Generator
The 125 MHz signal used for clocking the serial outputs is generated by the TX PLL block based on the user-provided TX_CLK. This clock should have a 100 ppm tolerance.
Internal Loopback
When EWRAP is set to a logic HIGH, the serial data stream generated by the transmitter is looped back to the receiver path, instead of going out to the DOUT pins. When in loopback mode, a static logic 1 is transmitted at the line driver (DOUT+ is HIGH and DOUT- is LOW).
Signal Detect
Signal detect block is used to sense the serial input data stream at pins DIN. If the serial input is lower than 50mV differentially, this block deasserts SIG_DET and sets the output, RX<9:0>, to all logic ones. When the serial input at pins DIN is greater than 50mV, the signal is directed to the receive path.
Equalizer and Slicer
The signal received from the line (DIN pins) is distorted by the cable bandwidth. In order to maintain a low bit-error rate, an equalizer is used to compensate for the signal loss. The slicer recovers the differential low-level signal to a CMOS-level single-ended signal, for clock recovery and data re-timing.
Clock Recovery
The serial input data stream contains both data and clock. The clock recovery block is used to extract both data and clocks from this input. In addition to data, two clocks of 62.5 MHz are recovered.
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Table 3. Absolute Maximun Ratings
Symbol VCC VIN,TTL VIN,HS_IN IOUT,TTL Tstg Tj Parameter Supply voltage TTL Input Voltage High-Speed Input Voltage TTL Output Source Current Storage Temperature Junction Operating Temperature -65 0 Min. -0.5 -0.7 2.0 Max. 5.0 VCC + 2.8 VCC 13 +150 +150 mA C V Units
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Table 4. Guaranteed Operating Rates TA = 0oC to +70oC, VCC = 3.15V to 3.45V
Parallel Clock Rate (MHz) Min. 124.0 Max. 126.0 Min. 1240 SerialBaud Rate (Mbaud) Max. 1260
Table 5. AC Electrical Characteristics TA = 0C to +70C, VCC = 3.15V to 3.45V
Symbol tr,REFCLK tf,REFCLK tr,TTL_IN tf,TTL_IN tr,TTL_OUT tf,TTL_OUT trs,HS_OUT tfs,HS_OUT VIP,HS_IN VOP,HS_
OUT (1)
Parameter REFCLK Rise Time, 0.8 to 2.0 Volts REFCLK Fall Time, 2.0 to 0.8 Volts Input TTL Rise Time, 0.8 to 2.0 Volts Input TTL Fall Time, 2.0 to 0.8 Volts Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load HS_OUT Single-Ended (DOUT+) Rise Time HS_OUT Single-Ended (DOUT+) Fall Time HS_IN Input Peak-to-Peak Differential Voltage HS_OUT Output Peak-to-Peak Differential Voltage
Min.
Typ.
Max. 2.4 2.4
Unit
2 2 1.5 1.1 85 85 200 1200 225 200 1200 1600 2.4 2.4 327 327 2000 2000
ns
ps
mV
Note: 1. Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-
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Table 6. DC Electrical Characteristics TA = 0C to +70C, VCC = 3.15V to 3.45V
Symbol VIH,TTL VIL,TTL VOH,TTL VOL,TTL IIH,TTL IIL,TTL ICC,TRX[1,2] Parameter TTL Input High Voltage Level, Guaranteed High Signal for All Inputs TTL Input Low Voltage Level, Guaranteed Low Signal for All Inputs TTL Output High Voltage Level, IOH = -12 mA TTL Output Low Voltage Level, IOL = 12 mA Input High Current, VIN = VCC, VCC = 3.45 V Input Low Current, VIN = 0V, VCC = 3.45 V Transceiver VCC Supply Current, TA = 25C 220 Min. 2 0 2.2 0 Typ. Max. 5.5 0.8 VCC 0.6 5 -5 A mA V Unit
Notes: 1. Measurement Conditions: Tested sending 1250 MBd PRBS 27-1 sequence from a serial Bit Error Rate Tester (BERT) with DOUT outputs terminated with 150 resistors to GND. 2. Typical values are at VCC = 3.3 volts.
Table 7. Transceiver Reference Clock Requirements TA = 0C to +70C, VCC = 3.15V to 3.45V
Symbol f Ftol Symm Parameter Nominal Frequency (for gigabit Ethernet Compliance) Frequency Tolerance Symmetry (Duty Cycle) -100 40 Min. Typ. 125 +100 60 Max. Unit MHz ppm %
Table 8. Transmitter Timing Characteristics TA = 0C to +70C, VCC = 3.15V to 3.45V
Symbol tsetup thold t_txlat[1] Parameter Setup Time to Rising Edge of TX_CLK Hold Time to Rising Edge of TX_CLK Transmitter Latency Min. 1.5 1.0 3.5 4.4 bits ns Typ. Max. Unit
Note: 1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit by clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the rising edge of the first bit transmitted).
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1.4V TX_CLK
2.0V TX<9:0> DATA
tSETUP tHOLD
DATA
DATA
DATA
DATA 0.8V
Figure 3. Transmitter Section Timing
DATA BYTE A
DATA BYTE B
DOUT T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 t_TXLAT TX<9:0> DATA BYTE B DATA BYTE C
TX_CLK
1.4V
Figure 4. Transmitter Latency
Table 9. Receiver Timing Characteristics TA = 0C to +70C, VCC = 3.15V to 3.45V
Symbol b_sync[1] f_lock tSETUP tHOLD tDUTY tA-B T_rxlat[2] Parameter Bit Sync Time Frequency Lock at Powerup Data Setup Before Rising Edge of RX_CLK Data Hold After Rising Edge of RX_CLK RX_CLK Duty Cycle RX_CLK Skew Receiver Latency 2.5 1.5 40 7.5 22.4 28.0 60 8.5 Min. Typ. Max. 2500 500 Unit bits s ns % ns ns bits
Notes: 1. This is the recovery for input phase jumps. 2. The receiver latency as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, either RBC1 or RBC0).
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tSETUP tHOLD
RX_CLK<1> 1.4V
2.0V RX<9:0>
K28.5
DATA
DATA
DATA
DATA
0.8V 2.0V
COM_DET 0.8V RX_CLK<0>
1.4V
tA-B
Figure 5. Receiver Section Timing
DATA BYTE C DIN R5 R6 R7 R8 R9 R0 R1 R2
DATA BYTE D R3 R4 R5 R6 R7 R8 R9 R2 R3 R4 R5
t_rxlat
RX<9:0>
DATA BYTE A
DATA BYTE D
RX_CLK<1>/<0>
1.4V
Figure 6. Receiver Latency
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Packaging Mechanical: 64-pin LQFP (FC)
.472 12.00 BSC Square
.394 10.00 BSC Square
.004 .008 0.09 0.20
GAUGE PLANE
0.25 mm
.018 0.45 .030 0.75
.039 1.00 REF
.063 1.60 Max.
.004 0.10
Seating Plane
.007 0.17 .010 0.27
.019 0.50 BSC
.002 .006 0.05 0.15
.053 .057 1.35 1.45
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
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Packaging Mechanical: 64-pin LQFP (FD)
.630 16.00 BSC Square
.551 14.00 BSC Square
.004 .008 0.09 0.20
GAUGE PLANE
0.25 mm
.018 0.45 .030 0.75
.039 1.00 REF
.063 1.60 Max.
.004 0.10
Seating Plane
.007 0.17 .010 0.27
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
.031 0.80 BSC
.002 .006 0.05 0.15
.053 .057 1.35 1.45
Ordering Information
Ordering Code PI90SD1636CFC PI90SD1636CFCE PI90SD1636CFD PI90SD1636CFDE Package Code FC FC FD FD Package Description 64-pin 10mm x10mm LQFP Pb-free & Green, 64-pin 10mm x10mm LQFP 64-pin 14mm x14mm LQFP Pb-free & Green, 64-pin 14mm x14mm LQFP
Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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Appendix A Gigabit Ethernet Transceiver
Pin Cross Reference Guide PI90SD1636C, VSC7123 and HDMP1636A/1646A
Summary:
Pericom Semiconductor's PI90SD1636C is functionally pin compatible with Vitesse's VSC7123 and Agilent's HDMP-1636A/46A. Minor differences exist amongst the parts regarding the use of certain pins that are used by the manufacturer for internal tests, as is further clarified below. These differences will not affect plug compatibility during normal operations.
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Pericom Pin # 1 2 3 4 6 7 8 9 11 12 13 5 10 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 PI90SD1636C GND_ESD TX<0> TX<1> TX<2> TX<3> TX<4> TX<5> TX<6> TX<7> TX<8> TX<9> VDD_ESD VDD_ESD GND_ESD GND_TXA NC NC VDD_TXA EWRAP VDD_TXD GND_TXD TX_CLK VDD_RXD EN_CDET GND_RXD SIG_DET NC VDD_RXD VDD_RX RX_CLK<1> RX_CLK<0> GND_RX GND_RXT
Vitesse VSC7123 VSSD T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 VDDD VDDD VSSD VSSA CAP0 CAP1 VDDA EWRAP VDDD VSSD REFCLK VDDD ENCDET VSSD SIGDET (Note 1) VDDD VDDT RCLKN RCLK VSST VSST
Agilent HDMP1636A/46A GND TX[0] TX[1] TX[2] TX[3] TX[4] TX[5] TX[6] TX[7] TX[8] TX[9] VCC VCC GND GND_TXA TXCAP1 TX_CAP0 VCC_TXA LOOPEN VCC GND REFCLK VCC ENBYTSYNC GND SIG_DET NC VCC VCC_RXTTL RBC1 RBC0 GND_RXTTL GND_RXTTL Connect to 3.3V Connect to 3.3V Connect to the ground plane. Connect to the ground plane. Pericom requires no external caps. External capacitor will not affect performance Pericom requires no external caps. External capacitor will not affect performance Connect to 3.3V Loop-back Enable when HIGH. Set LOW for normal operation Connect to 3.3V Connect to the ground plane 125MHz reference clock. Connect to 3.3V Comma Detect Enable (Active HIGH) Connect to the ground plane. Signal Detect (Active HIGH) NCTD0, No connect for normal operation. Connect to 3.3V Connect to 3.3V Receiver Byte Clock Receiver Byte Clock Connect to the ground plane Connect to the ground plane Comments Connect to the ground plane. 10-bit parallel data input pins.
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Pericom Pin # 34 35 36 38 39 40 41 43 44 45 37 42 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PI90SD1636C RX<9> RX<8> RX<7> RX<6> RX<5> RX<4> RX<3> RX<2> RX<1> RX<0> VDD_RXT VDD_RXT GND_RXT COM_DET NC NC VDD_RXF GND_RXF DINVDD_RXESD DIN+ VDD_RXESD GND_RXESD VDD_RXA GND_RXA VDD_RXA VDD_TX_ECL DOUTDOUT+ VDD_TX_HS GND_TX_HS
Vitesse VSC7123 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 VDDT VDDT VSST COMDET TDI TCK VDDD VSSD RXN/C (Note 2) RX+ TMS TRSTN VDDD VSSD VDDD VDDP TXTX+ VDDP VSSD
Agilent HDMP1636A/ 46A RX[9] RX[8] RX[7] RX[6] RX[5] RX[4] RX[3] RX[2] RX[1] RX[0] VCC_RXTTL VCC_RXTTL GND_RXTTL BYTSYNC RXCAP0 RXCAP1 VCC_RXA GND_RXA -DIN VCC Connect to 3.3V +DIN VCC GND VCC GND VCC VCC_TXECL -DOUT +DOUT VCC_TXHS GND_TXHS High-speed serial data input Connect to 3.3V Connect to the ground plane Connect to 3.3V Connect to the ground plane Connect to 3.3V Connect to 3.3V High-speed serial data output High-speed serial data output Connect to 3.3V Connect to the ground plane Connect to 3.3V Connect to 3.3V Connect to the ground plane Comma Detect ( Byte Sync) Pericom requires no external caps. External capacitor will not affect performance Pericom requires no external caps. External capacitor will not affect performance Connect to 3.3V Connect to the ground plane High-speed serial data input Comments Received Parallel Data Output
Notes: 1. For VSC7123, this pin is in high-impedance state in normal operation. 2. For VSC7123, this pin has no internal connection.
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